In the case of electrically writeable and erasable memories, a distinction is made between volatile and non-volatile memory cells. Non-volatile memory cells also include, by way of example, a so-called charge-trapping memory cell, which may be used, e.g., in a virtual ground NOR architecture and the construction of which is modified on the basis of a MOS field effect transistor (MOSFET), to the effect that a gate insulation layer has, for example, a layer stack having three layers. In the case of charge-trapping memory cells, typically an electrically non-conductive middle layer of the three layers is provided for trapping and storing charge carriers and the outer boundary layers prevent the charge carriers from flowing away from the middle layer, which is also referred to as the storage layer.
By means of suitable programming operating modes, in the case of the memory cell, charge carriers can be introduced into the storage layer in a defined manner in order to alter the electrical behavior of the memory cell in read operation. This programming of the memory cell 100 results in different charge states of the memory cell, which can be assigned equivalently to different logic states and can also be read out again in suitable read operation of the memory cell.
When a voltage is applied between the control gate and the substrate in read operation of the memory cell, the presence of charges in the storage layer alters the vertical electric field in the channel region in comparison with the state of the memory cell in which no charges are present in the storage layer. The vertical electric field in the channel region that results from the applied voltage and the electric field of the charge carriers in the case of an electrically charged storage layer alters the operating behavior of the memory cell in comparison with the operating behavior in the case of an uncharged storage layer. This is shown, e.g., by the fact that the threshold voltage VT of the transfer characteristic curve of this modified MOSFET arrangement is shifted to higher values when negative charge carriers are introduced. Correspondingly lower threshold voltages result when positive charge carriers are introduced.
A memory cell constructed in this way is also referred to as a SONOS memory cell (semiconductor-oxide-nitride-oxide semiconductor).
In the case of this memory cell, the boundary layers are usually embodied as oxide and the storage layer is usually embodied as nitride of the semiconductor material, usually silicon.
Alongside other methods, charge-trapping memory cells are programmed by means of so-called hot electrons (channel hot electrons, CHE) by introduction of electrons into the storage layer during programming, and can be erased, e.g., by means of so-called hot holes in that the negatively-charged electrons in the storage layer are compensated for by means of positively-charged holes.
A SONOS memory cell provided for a specific operating mode with a read voltage applied in the opposite sense to the programming operation (reverse read) and with a thickness of the boundary layers that is adapted to this operating mode is usually referred to as an NROM memory cell. The NROM memory cell is typically constructed symmetrically with regard to a first source/drain region and a second source/drain region. The NROM memory cell can be operated in at least two different operating modes from which at least two electrical quantities can be derived. These operating methods typically differ in the direction of the electrical voltages that are applied to the source/drain regions during the reading and programming of the memory cell.
By means of these two operating modes it is possible to program the memory cell into four different charge states and thus to store two bits since, in the case of programming operation in the first operating direction, from the first source/drain region to the second source/drain region, the charges are stored in the storage layer in a second charge storage region in the vicinity of the second source/drain region and, in the case of symmetrically reversed operation in the second operating direction, that is to say from the second source/drain region to the first source/drain region, charges are stored in the storage layer in the first charge storage region in the vicinity of the first source/drain region. During reading, the memory cell can be operated in such a way that the derived electrical quantities react particularly sensitively to charges present in one of the two charge storage regions of the charge storage layer and it is thus possible to define, e.g., four different logic states for storing two bits.
However, the introduction of charges into the first charge storage region, e.g., in the vicinity of the first source/drain region of such a memory cell causes alterations when reading out the electrical quantity during the operation of the memory cell in the second operating direction for detecting the amount of charge in the second charge storage region in the vicinity of the second source/drain region of the memory cell, and correspondingly vice versa.
This so-called crosstalk has a more pronounced effect, the greater the difference between the amounts of charge in the storage layer in the vicinity of the two source/drain regions. This crosstalk is reduced by means of suitable operating parameters such as, e.g., a higher voltage between the source/drain regions. However, as the technology is developed further, the effective channel length becomes smaller and, consequently, so does the physical distance between the charges on the two sides of a cell. This leads to greater crosstalk. It can, therefore, be expected that this crosstalk will cause problems during operation (in particular during read-out) to an increased extent in the future.
As described in US Application Publication No. 2005/0195650, crosstalk can be prevented, or greatly reduced, by means of altered operation of the memory cell.
In the case of this differential memory concept, greatly different amounts of charge at the two storage locations are avoided by virtue of the fact that the charge states are no longer directly assigned to the logic states, because the above-mentioned large differences in the amounts of charge between the two storage locations can arise with direct assignment.
In order to avoid this, the differential memory concept involves defining, e.g., two charge amount ranges that are small compared with the total charge amount range available for the programming of the memory cell. The charge states in the two charge storage regions are then either in an upper charge amount range, which is produced, e.g., by means of the difference between two upper charge states, or in a lower charge amount range, which is produced, e.g., by means of the difference between two lower charge states.
The two further logic states are then produced by means of programming in such a way that the charge states of the two charge storage regions differ in terms of magnitude by means of a value within one of the two defined charge amount ranges. The two further logic states are then produced by means of the sign of the difference when operating the memory cell in two different operating modes, e.g., by means of the channel region being operated in a first direction and by means of the channel region being operated in a second direction.
The effect of crosstalk is minimized with this programming by virtue of the fact that there are never large differences in the amounts of charge of the two charge storage regions or resulting threshold voltage differences during operation in the two operating modes. The threshold voltage of the memory cell serves as one example of an electrical quantity to be determined, which results from the charge states.
For determining the charge states of the memory cells, the at least two electrical quantities that result from the charge states in the at least two different operating modes of the memory cells are sequentially determined and provided since, in the case of the differential memory concept, at least one of the states results from the difference between the electrical quantities.
An evaluation circuit arrangement and an evaluation method for the assessment of electrical quantities provided that result from a memory operating concept with a varying mode of operation are required.